Conference Papers by S. A. A. Shah


R. Meyer, B. Farkas, S. A. A. Shah, and M. Berekovic
Transparent SystemC Model Factory for Scripting Languages
Design and Verification Conference (DVCon) United States 2017, February 27 - March 2, 2017 , San Jose, CA USA, 2017
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S. A. A. Shah, S. Horsinka, B. Farkas, R. Meyer, and M. Berekovic
Automatic Exploration of Hardware/Software Partitioning
Design and Verification Conference (DVCon) United States 2017, February 27 - March 2, 2017 , San Jose, CA USA, 2017
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S. A. A. Shah, B. Farkas, R. Meyer, and M. Berekovic
Accelerating MPSoC Design Space Exploration Within System-Level Frameworks
The IEEE Nordic Circuits and Systems Conference (NORCAS), 1-2 November 2016 Copenhagen, Denmark, 2016
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B. Farkas, S. A. A. Shah, J. Wagner, R. Meyer, R. Buchty, and M. Berekovic
An Open and Flexible SystemC to VHDL Workflow for Rapid Prototyping
Design and Verification Conference (DVCon) Europe 2016, October 19 - 20, 2016 Munich, Germany, 2016
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H. Al-Khalissi, S. A. A. Shah, and M. Berekovic
An Efficient Barrier Implementation for OpenMP-Like Parallelism on the Intel SCC
PDP '14: Proceedings of the 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, IEEE Computer Society, 2014, ISBN 978-1-4799-2729-6
DOI, ISBN, RIS, BibTex
S. A. A. Shah, J. Wagner, T. Schuster, and M. Berekovic
A lightweight-system-level power and area estimation methodology for application specific instruction set processors
Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014 24th International Workshop on, 2014
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